1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for scheduling a plurality of processing tools.
2. Description of the Related Art
A variety of processing tools are used to fabricate a semiconductor device. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular operating recipe. For example, a photolithography stepper may be used to form a patterned layer of photoresist (i.e. a mask) above a dielectric layer that has been deposited above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. The wafer is then provided to an etch tool that etches away portions of the dielectric layer corresponding to features in the mask to form the plurality of features above the surface of the wafer.
The characteristics of the features formed above the surface of the wafer depend in part on the processing tools that participated in forming the feature. For example, the width of an etch line on a wafer is typically defined by both the etching and photolithography processes. For example, a layer of material may be deposited above a wafer. Then a patterned layer of photoresist (e.g. a mask layer) is formed above the layer of material by a photolithography tool. An etching process is then performed on the underlying layer of material through the patterned masking layer to define a plurality of features, e.g. lines, in the underlying layer of material. Thus, errors in either the photolithography process used to form the patterned masking layer or the etching process may lead to errors in the features formed in the underlying layer.
Feedback control may be provided to some of the processing tools to control the characteristics of the features formed above the surface of the wafer. For example, the exposure dose used by a photolithography stepper may be adjusted to control the width of printed resist lines formed in the mask layer. However, various practical considerations, including cost, complexity, and the like, usually limit the number of processing tools that can be placed under feedback control in conventional processing systems. Thus, conventional processing systems typically rely upon predetermined process models to account for the characteristics of features formed by the processing tools. For example, a process model may be used to relate a development inspection critical dimension (DICD) of a feature in a mask layer to a final inspection critical dimension (FICD) of the corresponding feature when formed above the wafer, i.e. after the etching process is complete. Thus, the exposure dose used in the photolithography step may be selected so that, on average, the final inspection critical dimension (FICD) of etched lines formed above the wafers in a wafer lot processed by the photolithography stepper and the etching tool will be near a target value for the final inspection critical dimension (FICD) of such a feature.
In some process flow arrangements, a single tool may be used to supply wafers to a selected one of a plurality of other processing tools. For example, a photolithography stepper can form a mask layer over a wafer in approximately one minute, whereas an etching tool may take three to four minutes to etch the wafer. Thus, at least in part to maintain a desired wafer throughput, conventional etch process flows may include, for example, two or three photolithography stepper tools that provide masked wafers to six or seven etching tools. Such conventional processing systems typically rely upon a single process model to account for the characteristics of features formed by the processing tools. For example, a single process model may be used to relate development inspection critical dimensions (DICD) of features in patterned masking layers formed by the aforementioned two or three photolithography stepper tools to final inspection critical dimensions (FICD) of corresponding features formed by the aforementioned six or seven etching tools.
However, a single process model may not be sufficient to characterize features that are formed in process flows that lack a one-to-one correspondence between the processing tools in the process flow. For example, each photolithography stepper may form a mask layer having a different development inspection critical dimension (DICD). Moreover, each etch tool in the process flow may have a different etch bias so that the relationship between the development inspection critical dimension (DICD) and the final inspection critical dimension (FICD) may vary depending on the etching tool used to form the feature. Thus, the actual final inspection critical dimension (FICD) of features formed on the wafer may differ from the value predicted by the process model and may also vary depending upon the particular combination of photolithography stepper and/or etching tool used to form the mask layer and/or feature. Consequently, attempting to control the final inspection critical dimension (FICD) of features etched by the different etch tools by controlling the exposure dose in the photolithography stepper based upon a single process model for all combinations of the various processing tools may result in different feature size populations for each of the etching tools.
The present invention is directed to addressing the effects of one or more of the problems set forth above.